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CPU Signals Problem | |
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Consider the diagram in Figure 5.33 on p. 383. Assume that the CPU is executing the instruction
sw $8, 180($29)
Fill in the value of each indicated signal at the end of each cycle. If a control signal does not matter, record an X. If a data signal is unknown, record an X. Assume the memory cannot both read and write during the same cycle.
| Signal | Cycle 1 | Cycle 2 | Cycle 3 | Cycle 4 | ||||
| PCWriteCond | ||||||||
| PCWrite | ||||||||
| MemRead | ||||||||
| . . . |
| Signal | Cycle 1 | Cycle 2 | Cycle 3 | Cycle 4 | ||||
| PCWriteCond | 0 | 0 | 0 | 0 | ||||
| PCWrite | 1 | 0 | 0 | 0 | ||||
| IorD | 0 | X | X | 1 | ||||
| MemRead | 1 | X | X | 0 | ||||
| MemWrite | 0 | 0 | 0 | 1 | ||||
| MemtoReg | X | X | X | X | ||||
| IRWrite | 1 | 0 | 0 | 0 | ||||
| PCSource | 0 | X | X | X | ||||
| ALUOp | 00 | 00 | 00 | XX | ||||
| ALUSrcB | 01 | 11 | 10 | XX | ||||
| ALUSrcA | 0 | 0 | 1 | X | ||||
| RegWrite | 0 | 0 | 0 | 0 | ||||
| RegDst | X | X | X | X | ||||
| Instruction[5-0] | XXXXXX | 110100 | 110100 | 110100 | ||||
| Read register 2 | XXXXX | 01000 | 01000 | 01000 |