We will not cover the appendix, 7A.
Depending on time, we may abbreviate or skip part or all of 7.6–7.9.
Speedup of a component.
Text refers to this as Amdahl's Law, which I've only seen stated in a
more limited form.
If a system is modified to run faster (or slower), the speedup is just
the ratio of the old speedup to the new: S = To / Tn.
So if the new version takes half as long to complete, the speedup is 2.
The faster the newer version is (the less time it takes), the greater
We assume that the system speedup results from
speeding up some component of
interest, whose running time changes from to to tn.
The speedup of that component is given as k = to / tn.
Since the faster system speed is achieved by replacing the old
version of the
COI with the new one,
Tn = To − to + tn.
The portion of the total (original)
used by the COI is given by f = to / To.
Put on your algebra hat:
ToTo − to + tn
1 − f +
(1 − f) + f/k
If f is small, a large k doesn't help much.
Speeding up the CPU doesn't help much if your system is spending most
of its time doing I/O. And conversely.
PC Bus Layout
Devices have registers which can be fetched and stored.
Some registers may contain data being stored, fetched, or displayed.
Other registers contain device status. Often, individual
bits mean different things: Printer status register may have
on-line, paper present, busy printing, etc.
Some stores or fetches have side-effects. For instance, storing
printer register may cause the character to be printed.
Some memory addresses are re-directed to device registers.
CPU can communicate with regular store and fetch instructions.
Device registers are assigned port numbers, an addressing space
separate from memory.
CPU can communicate with devices using in and out instructions, which
are like store and fetch.
(If you recall, Marie has input and output instructions, but only one
The book confuses these terms with control methods.
What is needed?
Devices must be given data to display or record.
Data from the device must be moved to or the CPU to use.
Lots of delay and waiting.
Keystrokes or networking packets arrive without warning.
There is a long delay between requesting a disk sector and the
availability of the data.
After a device accepts some data, there may be a long processing
delay before it may accept more, or take some other action.
Some operations, disks particularly, may involve a series of
steps with waits between.
The CPU directly commands all steps.
It must frequently poll devices so it knows what to do.
Periodically ask the keyboard if there is a character in its
After asking for a disk sector, repeatedly ask the drive if the
data is available.
Very inefficient: CPU wastes a lot of time with “are we there yet?”
Devices notify the CPU of changes in status.
Sends an interrupt signal to the CPU. The service routine
manipulates the device.
The CPU can work on other things while the I/O works.
For instance, ask the disk for a sector and to interrupt when
Work on something else.
When the interrupt occurs, retrieve the contents of the sector.
Typically, the O/S handles the interrupts and lets a user program
run while waiting on devices.
Direct Memory Access I/O.
The DMA controller is a separate processor.
The CPU gives it a block to transfer. It does so, and
interrupts the CPU when done.
From the CPU's viewpoint, it groups several interrupting operations
I've never seen anyone else put the registers describing the
block in the CPU rather than the DMA controller itself.
Shared data buses.
The device that directs the operation of a bus is the
In simplest case, only one device attached to a bus is master, but
here the CPU and DMA must share.
If the DMA controller is mastering, the CPU will wait. Memory units
can usually wait, but I/O device timing is often critical. Called
More advanced DMA controller.
A channel runs a “channel program”, which allows it to perform more general
operations than the DMA transfer-a-block.
Usually disks or other storage devices.
Transfer a fixed-size block at a time.
Typically 512 bytes for a hard drive.
2K for a CD-ROM.
Usually can seek a particular block before transfer.
Tapes are block devices that cannot seek.
Transfer a byte at a time. Keyboard, mouse.
Transfer variable blocks. Network card.
Each horizontal line represents several lines.
Address and data lines may be shared.
Bus uses a share clock which synchronizes all operations.
One of the bus lines is a central clock which
synchronizes all operations.
All connected devices must use the same clock (and be of similar speed).
Limits either speed or length.
Connected devices have independent clocks.
Operations must by synchronized using a handshake protocol,
much like a network connection.
Works better to connect devices of various speeds.
Timing diagrams show the handshake interaction. Often, one change
must wait for another.